High speed input/output (I/O) pins require a low capacitance which puts severe constraints on any electrostatic discharge (ESD) circuit used to protect the I/O pins. Unfortunately, the resistance of many low capacitance ESD circuits is relatively high with the result that the ESD circuit provides only marginal ESD protection for positive zaps.
A typical ESD protection circuit 100 is shown in FIG. 1. Circuit 100 comprises a first diode 10 and a silicon controlled rectifier (SCR) 20 connected in series between an input node or lead 30 and a ground node 40 and a second diode 50 connected between input node 30 and ground node 40. An anode of the first diode is connected to input node 30 and an anode of the second diode is connected to ground node 40. In this arrangement, a positive zap is discharged through the first diode and SCR; and a negative zap is discharged through the second diode.
The first diode illustratively is formed by a PN junction between a heavily doped region of a first conductivity type and a well region of a second conductivity type. The second diode is formed by a PN junction between a heavily doped region of the second conductivity type and a well region of the first conductivity type. Preferably the first conductivity type is P and the second conductivity type is N.
Illustratively, the first diode has a capacitance of 24 femtoFarads (fF), the SCR has a capacitance of 150 fF and the second diode has a capacitance of 28 fF. As a result, the capacitance of the series combination of the first diode and SCR is 21 fF (24·150/(24+150)) and the total capacitance of the parallel combination of the first diode and SCR with the second diode is 49 fF (21+28).